As integrated circuit continue to scale, design rules get smaller and process margins are reduced. To keep deep source drain implants from causing short channel effects, sidewall spacers are used to provide sufficient distance between the transistor channel and the deep source drain to avoid punchthrough. However, as the space between transistors sharing the same active is scaled the space between the sidewall spacers on adjacent transistors may become too small to form high quality silicide. This may result in higher contact resistance when a contact falls on poorly formed silicide. In addition, the contact etch may etch away a portion of the sidewalls causing the contact to land on unsilicided active area resulting in an additional increase in contact resistance. Since contact resistance and active resistance is in series with the transistor, this additional series resistance may degrade transistor performance.